Snakes!
The first game on my FPGA platform
I have decided to make a game for the FPGA Computer. My friend gave me his Pascal implementation of the Snakes game and I have ported it into the FPGA Assembler. Not an easy task, but it works now:
7
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6
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5
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4
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3
|
2
|
1
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0
|
|
Foreground color,
inverted
|
|
Background color
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||||
|
|
r
|
g
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b
|
r
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g
|
b
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Group number
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Group name
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Group members
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Group description
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0
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NOP/MOV/
IN/OUT/PUSH/
POP/RET/IRET/
HALT/SWAP |
nop
mov reg, xx
mov reg, reg
in reg, [xx]
out [xx], reg
push reg
push xx
pop reg
ret
iret
swap halt
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The most general group.
Deals with putting values into registers, exchanging values between registers, I/O
operations, stack operations, returning from subroutines, and register content swapping. NOP
and HALT are also in this group.
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1
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JUMP
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j xx
jc xx
jnc xx
jz xx
jnz xx
jo xx
jno xx
jp xx
jnp xx
jg xx jge xx js xx jse xx |
Jump to the given
location.
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2
|
CALL
|
call xx
callc xx
callnc xx
callz xx
callnz xx
callo xx
callno xx
callp xx
callnp xx
callg xx callge xx calls xx callse xx |
Calling subroutine. Puts
the return address on the stack before jumping to the subroutine. Needs to call RET when
returning from the subroutine.
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3
|
LOAD/STORE
|
ld reg, [xx]
ld reg, [reg]
ld reg, [reg + xx]
ld.b reg, [xx]
ld.b reg, [reg]
ld.b reg, [reg + xx]
st [xx], reg
st [reg], reg
st [reg + xx], reg
st.b [xx], reg
st.b [reg], reg
st.b [reg + xx], reg
|
Load from memory into
the register
destination: register
source: memory address
given by the number, or by the register, or by the register+number.
Store the given register
into the memory location
destination: memory
location given by the number, or by the register, or by the register+number.
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4
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ADD/SUB
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add reg, reg
add reg, xx
add reg, [reg]
add reg, [xx]
add reg, [reg + xx]
add.b reg, [reg]
add.b reg, [xx]
add.b reg, [reg +
xx]
sub reg, reg
sub reg, xx
sub reg, [reg]
sub reg, [xx]
sub reg, [reg + xx]
sub.b reg, [reg]
sub.b reg, [xx]
sub.b reg, [reg +
xx]
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Add and sub group.
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5
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AND/OR
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and reg, reg
and reg, xx
and reg, [reg]
and reg, [xx]
and reg, [reg + xx]
and.b reg, [reg]
and.b reg, [xx]
and.b reg, [reg +
xx]
or reg, reg
or reg, xx
or reg, [reg]
or reg, [xx]
or reg, [reg + xx]
or.b reg, [reg]
or.b reg, [xx]
or.b reg, [reg + xx]
|
And / or group.
|
6
|
XOR
|
xor reg, reg
xor reg, xx
xor reg, [reg]
xor reg, [xx]
xor reg, [reg + xx]
xor.b reg, [reg]
xor.b reg, [xx]
xor.b reg, [reg +
xx]
|
Xor group.
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7
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SHL/SHR
|
shl reg, reg
shl reg, xx
shl reg, [reg]
shl reg, [xx]
shl reg, [reg + xx]
shl.b reg, [reg]
shl.b reg, [xx]
shl.b reg, [reg +
xx]
shr reg, reg
shr reg, xx
shr reg, [reg]
shr reg, [xx]
shr reg, [reg + xx]
shr.b reg, [reg]
shr.b reg, [xx]
shr.b reg, [reg +
xx]
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Shift group.
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8
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MUL/DIV
|
mul reg, reg
mul reg, xx
mul reg, [reg]
mul reg, [xx]
mul reg, [reg + xx]
mul.b reg, [reg]
mul.b reg, [xx]
mul.b reg, [reg +
xx]
div reg, reg
div reg, xx
div reg, [reg]
div reg, [xx]
div reg, [reg + xx]
div.b reg, [reg]
div.b reg, [xx]
div.b reg, [reg +
xx]
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Multiply / divide group.
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9
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INC/DEC
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inc reg
inc [reg]
inc [xx]
inc [reg + xx]
inc.b [reg]
inc.b [xx]
inc.b [reg + xx]
dec reg
dec [reg]
dec [xx]
dec [reg + xx]
dec.b [reg]
dec.b [xx]
dec.b [reg + xx]
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Increment and decrement
group.
|
10
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CMP/NEG
|
cmp reg, reg
cmp reg, xx
cmp reg, [reg]
cmp reg, [xx]
cmp reg, [reg + xx]
cmp.b reg, [reg]
cmp.b reg, [xx]
cmp.b reg, [reg +
xx]
neg reg
neg [reg]
neg [xx]
neg [reg + xx]
neg.b [reg]
neg.b [xx]
neg.b [reg + xx]
|
Compare / negate group.
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from
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to
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what
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group
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bbbb
0-7: r0-r7
8-sp
9-h
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bbbb
0-7: r0-r7
8-sp
9-h
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0000
0=>mov regx, regy
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0000
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address
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content
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1000
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0x12
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1001
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0x34
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7
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6
|
5
|
4
|
3
|
2
|
1
|
0
|
|
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Foreground color,
inverted
|
Background color
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||||
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r
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g
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b
|
r
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g
|
b
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Address
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Description
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64
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Received byte from the
RX part of the UART (use the IN instruction).
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65
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0 if the TX part of the
UART is free to send a byte, 1 if TX part is busy.
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66
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Byte to be sent must be
placed here using the OUT instruction.
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